Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 197)

Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDW
3-137 Instruction Set SPRU733
Increments and decrements default to 1 and offsets default to 0 when no
bracketed register or constant is specified. Loads that do no modification to the
baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst5 offset
is left-shifted by 2. Parentheses, ( ), can be used to set a nonscaled, constant
offset. For example, LDW (.unit) *+baseR (12) dst represents an offset of
12 bytes; whereas, LDW (.unit) *+baseR [12] dst represents an offset of
12 words, or 48 bytes. You must type either brackets or parentheses around
the specified offset, if you use the optional offset parameter.
Word addresses must be aligned on word (two LSBs are 0) boundaries.
Execution if (cond) mem → dst
else nop
Pipeline
Stage
E1 E2 E3 E4 E5
Read baseR
offsetR
Written baseR dst
Unit in use .D
Instruction Type Load
Delay Slots 4 for loaded value
0 for address modification from pre/post increment/decrement
For more information on delay slots for a load, see Chapter 4.
See Also LDB, LDDW, LDH
Pipeline