Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 336)

Pipeline Operation Overview
Pipeline 4-4 SPRU733
Figure 4−3(a) shows the decode phases in sequential order from left to right.
Figure 4−3(b) shows a fetch packet that contains two execute packets as they
are processed through the decode stage of the pipeline. The last six instruc-
tions of the fetch packet (FP) are parallel and form an execute packet (EP).
This EP is in the dispatch phase (DP) of the decode stage. The arrows indicate
each instruction’s assigned functional unit for execution during the same cycle.
The NOP instruction in the eighth slot of the FP is not dispatched to a functional
unit because there is no execution associated with it.
The first two slots of the fetch packet (shaded below) represent an execute
packet of two parallel instructions that were dispatched on the previous cycle.
This execute packet contains two MPY instructions that are now in decode
(DC) one cycle before execution. There are no instructions decoded for the .L,
.S, and .D functional units for the situation illustrated.
Figure 4−3. Decode Phases of the Pipeline
(b)
DC DP
(a)
DP
32 32 32 32 32 32 32 32
NOP † ADDK STW STW ADD
DC MPYH MPYH
.L1 .S1 .D1 .M1 .L2 .S2 .D2 .M2
Decode
ADD
Functional
units
† NOP is not dispatched to a functional unit.