Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 301)

Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STH
3-241 Instruction Set SPRU733
Increments and decrements default to 1 and offsets default to zero when no
bracketed register or constant is specified. Stores that do no modification to
the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst5
offset is left-shifted by 1. Parentheses, ( ), can be used to set a nonscaled,
constant offset. You must type either brackets or parentheses around the
specified offset, if you use the optional offset parameter.
Halfword addresses must be aligned on halfword (LSB is 0) boundaries.
Execution if (cond) src → mem
else nop
Pipeline
Stage
E1
Read baseR, offsetR, src
Written baseR
Unit in use .D2
Instruction Type Store
Delay Slots 0
For more information on delay slots for a store, see Chapter 4.
See Also STB, STW
Example 1 STH .D1 A1,*+A10(4)
Before
instruction
1 cycle after
instruction
3 cycles after
instruction
A1 9A32 7634h A1 9A32 7634h A1 9A32 7634h
A10 0000 0100h A10 0000 0100h A10 0000 0100h
mem 104h 1134h mem 104h 1134h mem 104h 7634h
Pipeline