1 memory stalls – Texas Instruments TMS320C67X/C67X+ DSP User Manual
Page 393
Performance Considerations
4-61
Pipeline
SPRU733
Depending on the type of memory and the time required to complete an
access, the pipeline may stall to ensure proper coordination of data and
instructions. This is discussed in section 4.4.3.1.
In the instance where multiple accesses are made to a single ported memory,
the pipeline will stall to allow the extra access to occur. This is called a memory
bank hit and is discussed in section 4.4.3.2.
4.4.3.1 Memory Stalls
A memory stall occurs when memory is not ready to respond to an access from
the CPU. This access occurs during the PW phase for a program memory
access and during the E3 phase for a data memory access. The memory stall
causes all of the pipeline phases to lengthen beyond a single clock cycle,
causing execution to take additional clock cycles to finish. The results of the
program execution are identical whether a stall occurs or not. Figure 4−32
illustrates this point.
Figure 4−32. Program and Data Memory Stalls
Clock cycle
Fetch
packet
(FP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
БББ
БББ
n
PG
PS
PW
PR
DP
DC
E1
E2
ЙЙ
ЙЙ
E3
E4
E5
БББ
БББ
n+1
БББ
БББ
PG
PS
PW
PR
DP
DC
E1
E2
E3
E4
БББ
БББ
n+2
БББ
БББ
ББ
ББ
PG
PS
PW
PR
DP
Program
DC
E1
E2
E3
БББ
БББ
n+3
PG
PS
PW
PR
memory stall
DP
DC
Data
E1
E2
БББ
БББ
n+4
PG
PS
ЙЙЙ
ЙЙЙ
PW
PR
DP
memory stall
DC
E1
ÁÁÁ
n+5
PG
PS
PW
PR
DP
DC
БББ
БББ
n+6
БББ
БББ
PG
PS
PW
PR
DP
БББ
БББ
n+7
БББ
БББ
БББ
БББ
PG
PS
PW
PR
БББ
БББ
n+8
БББ
БББ
БББ
БББ
БББ
БББ
PG
PS
PW
БББ
БББ
n+9
БББ
БББ
БББ
БББ
БББ
БББ
ББ
ББ
БББ
БББ
БББ
БББ
ББ
ББ
PG
PS
ÁÁÁ
n+10
БББ
БББ
БББ
ББ
БББ
БББ
ББ
БББ
PG