Texas Instruments TMS320C67X/C67X+ DSP User Manual
Page 375
Functional Unit Constraints
4-43
Pipeline
SPRU733
Table 4−27 shows the instruction constraints for MPYID instructions executing
on the .M unit.
Table 4−27. MPYID .M-Unit Instruction Constraints
Instruction Execution
Cycle
1
2
3
4
5
6
7
8
9
10
11
MPYID
R
R
R
R
W
W
Instruction Type
Subsequent Same-Unit Instruction Executable
16 × 16 multiply
Xr
Xr
Xr
n
n
n
Xw
Xw
n
n
4-cycle
Xr
Xr
Xr
Xu
Xw
Xw
n
n
n
n
MPYI
Xr
Xr
Xr
n
n
n
n
n
n
n
MPYID
Xr
Xr
Xr
n
n
n
n
n
n
n
MPYDP
Xr
Xr
Xr
Xu
Xu
Xu
n
n
n
n
MPYSPDP
Xr
Xr
Xr
Xw
Xu
Xu
n
n
n
n
MPYSP2DP
Xr
Xr
Xr
Xw
Xw
Xw
n
n
n
n
Instruction Type
Same Side, Different Unit, Both Using Cross Path Executable
Single-cycle
Xr
Xr
Xr
n
n
n
n
n
n
n
Load
n
n
n
n
n
n
n
n
n
n
Store
n
n
n
n
n
n
n
n
n
n
DP compare
Xr
Xr
Xr
n
n
n
n
n
n
n
2-cycle DP
Xr
Xr
Xr
n
n
n
n
n
n
n
Branch
Xr
Xr
Xr
n
n
n
n
n
n
n
4-cycle
Xr
Xr
Xr
n
n
n
n
n
n
n
INTDP
Xr
Xr
Xr
n
n
n
n
n
n
n
ADDDP/SUBDP
Xr
Xr
Xr
n
n
n
n
n
n
n
Legend:
= E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
n
= Next instruction can enter E1 during cycle; Xr = Next instruction cannot enter E1 during cycle−read/
decode constraint; Xw = Next instruction cannot enter E1 during cycle−write constraint; Xu = Next instruction cannot
enter E1 during cycle−other resource conflict