Texas Instruments TMS320C67X/C67X+ DSP User Manual
Page 458
Index
Index-4
SPRU733
D
DA1 and DA2 2-7
data address paths 2-7
DC pipeline phase 4-3
DCC bits 2-13
decoding instructions 4-3
delay slots 3-14
DEN1 bit
in FADCR 2-24
in FAUCR 2-27
in FMCR 2-31
DEN2 bit
in FADCR 2-24
in FAUCR 2-27
in FMCR 2-31
detection and processing, interrupts 5-16
disabling an individual interrupt 5-13
disabling maskable interrupts globally 5-12
DIV0 bit 2-27
double-precision data format 3-9
DP compare instruction, pipeline operation 4-27
DP compare instructions, .S-unit instruction
constraints 4-35
DP pipeline phase 4-3
DPINT instruction 3-104
DPSP instruction 3-106
DPTRUNC instruction 3-108
E
E1 phase program counter (PCE1) 2-22
E1−E5 pipeline phases 4-5
EN bit 2-13
enabling an individual interrupt 5-13
enabling maskable interrupts globally 5-12
execute packet, pipeline operation 4-56
execution notations 3-2
EXT instruction 3-110
extract and sign-extend a bit field (EXT) 3-110
extract and zero-extend a bit field (EXTU) 3-113
EXTU instruction 3-113
F
TMS320C67x DSP 1-4
TMS320C67x+ DSP 1-4
fetch packet 3-16
fetch packet (FP) 5-7
fetch packets
fully parallel 3-17
fully serial 3-17
partially serial 3-18
fetch pipeline phase 4-2
floating-point adder configuration register
(FADCR) 2-23
floating-point auxiliary configuration register
(FAUCR) 2-27
floating-point multiplier configuration register
(FMCR) 2-31
floating-point operands
double precision (DP) 3-9
single precision (SP) 3-9
FMCR 2-31
four-cycle instructions, pipeline operation 4-25
functional unit to instruction mapping B-1
functional units 2-5
G
general-purpose register files
cross paths 2-6
data address paths 2-7
description 2-2
memory, load, and store paths 2-6
GIE bit 2-13
H
HPEINT bits 2-21
I
ICn bit 2-16
ICR 2-16
IDLE instruction 3-116
IEEE standard formats 3-9