4 .d-unit instruction constraints – Texas Instruments TMS320C67X/C67X+ DSP User Manual
Page 384
Functional Unit Constraints
Pipeline
4-52
SPRU733
4.3.4 .D-Unit Instruction Constraints
Table 4−36 shows the instruction constraints for load instructions executing on
the .D unit.
Table 4−36. Load .D-Unit Instruction Constraints
Instruction Execution
Cycle
1
2
3
4
5
6
Load
RW
W
Instruction Type
Subsequent Same-Unit Instruction Executable
Single-cycle
n
n
n
n
n
Load
n
n
n
n
n
Store
n
n
n
n
n
Instruction Type
Same Side, Different Unit, Both Using Cross Path Executable
16 × 16 multiply
n
n
n
n
n
MPYI
n
n
n
n
n
MPYID
n
n
n
n
n
MPYDP
n
n
n
n
n
Single-cycle
n
n
n
n
n
DP compare
n
n
n
n
n
2-cycle DP
n
n
n
n
n
Branch
n
n
n
n
n
4-cycle
n
n
n
n
n
INTDP
n
n
n
n
n
ADDDP/SUBDP
n
n
n
n
n
Legend:
= E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
n
= Next instruction can enter E1 during cycle