Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 455)

Index
Index-1 SPRU733
Index
1X and 2X paths 2-6
2-cycle DP instructions, .S-unit instruction
constraints 4-36
4-cycle instructions
.L-unit instruction constraints 4-49
.M-unit instruction constraints 4-41
A
A4 MODE bits 2-10
A5 MODE bits 2-10
A6 MODE bits 2-10
A7 MODE bits 2-10
ABS instruction 3-38
ABSDP instruction 3-40
absolute value
floating-point
double-precision (ABSDP) 3-40
single-precision (ABSSP) 3-42
with saturation (ABS) 3-38
ABSSP instruction 3-42
actions taken during nonreset interrupt
processing 5-18
actions taken during RESET interrupt
processing 5-20
add
floating-point
double-precision (ADDDP) 3-56
single-precision (ADDSP) 3-60
signed 16-bit constant to register (ADDK) 3-59
two 16-bit integers on upper and lower register
halves (ADD2) 3-65
using byte addressing mode (ADDAB) 3-48
using doubleword addressing mode
(ADDAD) 3-50
using halfword addressing mode (ADDAH) 3-52
using word addressing mode (ADDAW) 3-54
with saturation, two signed integers
(SADD) 3-205
without saturation
two signed integers (ADD) 3-44
two unsigned integers (ADDU) 3-63
ADD instruction 3-44
add instructions
using circular addressing 3-32
using linear addressing 3-30
ADD2 instruction 3-65
ADDAB instruction 3-48
ADDAD instruction 3-50
ADDAH instruction 3-52
ADDAW instruction 3-54
ADDDP instruction 3-56
ADDDP instruction
.L-unit instruction constraints 4-51
.S-unit instruction constraints 4-38
pipeline operation 4-28
ADDK instruction 3-59
address generation for load/store 3-32
address paths 2-7
addressing mode 3-30
circular mode 3-31
linear mode 3-30
addressing mode register (AMR) 2-10
ADDSP instruction 3-60
.S-unit instruction constraints 4-37
ADDU instruction 3-63
AMR 2-10
AND instruction 3-67
applications, TMS320 DSP family 1-3
architecture, TMS320C67x DSP 1-7
arithmetic shift left (SHL) 3-213
arithmetic shift right (SHR) 3-215