Portion of figure 4−7 – Texas Instruments TMS320C67X/C67X+ DSP User Manual
Page 342
Pipeline Operation Overview
Pipeline
4-10
SPRU733
Registers used by the instructions in E1 are shaded in Figure 4−7. The multi-
plexers used for the input operands to the functional units are also shaded in
the figure. The bold crosspaths are used by the MPY and SUBSP instructions.
Figure 4−7. Pipeline Phases Block Diagram
CMPLTSP
DP
PR
PW
PS
PG
32
32
32
32
32
32
32
32
256
ABSSP
SUB
LDDW
MVK
CMPLTSP
ABSSP
B
ADDSP
SUBSP
SUB
ZERO
LDDW
LDDW
ABSSP CMPLTSP
ADDSP
MV
LDDW
B
MPYSP
SUBSP
LDDW
Register file A
Register file B
Data 2
Data 1
32
32
32
32
(byte addressable)
Internal data memory
Data address 2
Data address 1
9
8
7
6
5
4
3
2
1
0
16
16
16
16
Data memory interface control
DC
MPYSP
ADDSP
LDDW
MPYSP
32
E1
.L1
ADDSP
.S1
ABSSP
.D1
.M1
MPYSP
0
1
3
5 4
2
6
8 7
10
12 11
9
14
15
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
.L2
SUBSP
.S2
.D2
MPYSP
.M2
Fetch
Decode
Execute
ADDSP
SUBSP
ADDSP
ADDSP
SUBSP
MVK
ADDSP
MPYSP CMPLTSP
ADDSP
ABSSP
LDDW
MPYSP
MPYSP
MPYSP
MPYSP
MPYSP
MPYSP
MPYSP
MPYSP
ZERO