Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 92)

Addressing Modes
Instruction Set 3-32 SPRU733
3.8.2.2 ADDA and SUBA Instructions
As with linear address arithmetic, offsetR/cst is shifted left by 3, 2, 1, or 0
according to the data size, and is then added to or subtracted from baseR to
produce the final address. Circular addressing modifies this slightly by only
allowing bits N through 0 of the result to be updated, leaving bits 31 through
N + 1 unchanged after address arithmetic. The resulting address is bounded
to 2
(N + 1) range, regardless of the size of the offsetR/cst.
The circular buffer size in AMR is not scaled; for example, a block size of 8 is
8 bytes, not 8 times the data size (byte, halfword, word). So, to perform circular
addressing on an array of 8 words, a size of 32 should be specified, or N = 4.
Example 3−5 shows an ADDAH performed with register A4 in circular mode
and BK0 = 4, so the buffer size is 32 bytes, 16 halfwords, or 8 words. The value
in AMR for this example is 0004 0001h.
Example 3−5. ADDAH Instruction in Circular Mode
ADDAH .D1 A4,A1,A4
Before ADDAH 1 cycle after ADDAH
A4 0000 0100h A4 0000 0106h
A1 0000 0013h A1 0000 0013h
Note: 13h halfwords is 26h bytes. 26h bytes is 6 bytes beyond the 32-byte (20h) boundary 100h−11Fh; thus, it is wrapped
around to (126h − 20h = 106h).
3.8.3 Syntax for Load/Store Address Generation
The C64x DSP has a load/store architecture, which means that the only way
to access data in memory is with a load or store instruction. Table 3−10 shows
the syntax of an indirect address to a memory location. Sometimes a large off-
set is required for a load/store. In this case, you can use the B14 or B15 register
as the base register, and use a 15-bit constant (ucst15) as the offset.
Table 3−11 describes the addressing generator options. The memory address
is formed from a base address register (baseR) and an optional offset that is
either a register (offsetR) or a 5-bit unsigned constant (ucst5).