Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 241)

Move Between Control File and Register File MVC
3-181 Instruction Set SPRU733
Execution if (cond) src2 → dst
else nop
Note:
The MVC instruction executes only on the B side (.S2).
Refer to the individual control register descriptions for specific behaviors and
restrictions in accesses via the MVC instruction.
Pipeline
Stage
E1
Read src2
Written dst
Unit in use .S2
Instruction Type Single-cycle
Any write to the ISR or ICR (by the MVC instruction) effectively has one delay
slot because the results cannot be read (by the MVC instruction) in the IFR until
two cycles after the write to the ISR or ICR.
Delay Slots 0
Example MVC .S2 B1,AMR
Before instruction 1 cycle after instruction
B1 F009 0001h B1 F009 0001h
AMR 0000 0000h AMR 0009 0001h
Note:
The six MSBs of the AMR are reserved and therefore are not written to.
Pipeline