Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 352)

Pipeline Execution of Instruction Types
Pipeline 4-20 SPRU733
4.2.4 Load Instructions
Data loads require five, E1−E5, of the pipeline execute phases to complete
their operations (see Table 4−6). Figure 4−14 shows the fetch, decode, and
execute phases of the pipeline that the load instructions use.
Figure 4−15 shows the operations occurring in the pipeline phases for a load.
In the E1 phase, the data address pointer is modified in its register. In the E2
phase, the data address is sent to data memory. In the E3 phase, a memory
read at that address is performed.
Table 4−6. Load Instruction Execution
Pipeline Stage E1 E2 E3 E4 E5
Read baseR
offsetR
Written baseR dst
Unit in use .D
Figure 4−14. Load Instruction Phases
PG PS PW PR DP DC E1 E2 E3 E4 E5
4 delay slots
Address
modification