Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 345)

Pipeline Execution of Instruction Types
4-13 Pipeline SPRU733
Table 4−2. Execution Stage Length Description for Each Instruction Type (Continued)
Instruction Type
Execution
phases
2-Cycle DP 4-Cycle INTDP DP Compare
E1 Compute the lower
results and write to
register Read sources and
start computation Read sources and start
computation Read lower sources
and start computation
E2 Compute the upper
results and write to
register Continue computation Continue computation Read upper sources,
finish computation,
and write results to
register
E3 Continue computation Continue computation
E4 Complete computation
and write results to
register Continue computation
and write lower results
to register
E5 Complete computation
and write upper results
to register
E6
E7
E8
E9
E10
Delay slots 1 3 4 1
Functional
unit latency 1 1 1 2
Notes: 1) This table assumes that the condition for each instruction is evaluated as true. If the condition is evaluated as false,
the instruction does not write any results or have any pipeline operation after E1.
2) NOP is not shown and has no operation in any of the execution phases.