Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 350)

Pipeline Execution of Instruction Types
Pipeline 4-18 SPRU733
4.2.3 Store Instructions
Store instructions require phases E1 through E3 of the pipeline to complete
their operations (see Table 4−5). Figure 4−12 shows the fetch, decode, and
execute phases of the pipeline that the store instructions use.
Figure 4−13 shows the operations occurring in the pipeline phases for a store
instruction. In the E1 phase, the address of the data to be stored is computed.
In the E2 phase, the data and destination addresses are sent to data memory.
In the E3 phase, a memory write is performed. The address modification is
performed in the E1 stage of the pipeline. Even though stores finish their
execution in the E3 phase of the pipeline, they have no delay slots. There is
additional explanation of why stores have zero delay slots in section 4.2.4.
Table 4−5. Store Instruction Execution
Pipeline Stage E1 E2 E3
Read baseR,
offsetR
src
Written baseR
Unit in use .D2
Figure 4−12. Store Instruction Phases
PG PS PW PR DP DC E1 E2 E3
Address
modification