Texas Instruments MSC1210 - Manual (Page 110)

Events That Can Trigger Interrupts
10-4
In other words, the MSC1210 can be configured so that any of the events in
Table 10−1, ranging from a simple Timer 0 overflow to a watchdog or ADC conver-
sion event, will trigger an interrupt calling the appropriate interrupt handler routines.
Interrupt/Event—The first column of Table 10−1 indicates the name of the
event, or interrupt, in question.
Addr—The second column indicates the address that to which the MSC1210
will jump, to service the interrupt when it occurs, assuming it has been enabled.
This is where the interrupt code must be placed in code memory. It is common
practice to place an LJMP at the address specified for the interrupt, which
jumps to the actual code somewhere else in code memory, because there are
only eight bytes of memory for each routine.
Priority—The third column indicates the natural priority of the interrupt. This
is the order in which interrupts will be checked. If two or more interrupts occur
simultaneously, the interrupt with a higher interrupt priority (i.e., that appears
first in the list) will be serviced first.
Flag—The fourth column indicates the flag that, when set, will trigger the spe-
cified interrupt. These flags are normally set by the MSC1210 automatically
to indicate an interrupt condition. You can, however, set these bits manually
to trigger the corresponding interrupt, except in the case of the auxiliary inter-
rupts, which are serviced at 33
H
.
Enable—The fifth column indicates the bit that must be set in order to enable
the given interrupt. If this bit is not set, the interrupt flag will not provoke an in-
terrupt.
Priority Control—The final column indicates the bit that controls that interrupt
priority as either high or low priority.
Note:
The interrupts that are serviced at 0033
H
are always of the highest priority
and that priority may not be modified.