Texas Instruments MSC1210 - Manual (Page 249)

Summation/Shifter
17-21
Keil Simulator
The non-editable text window across from the acc count shows the current
number of data samples accumulated into the summation registers for the cur-
rent accumulate & shift cycle. The summation/shifter module depicted in
Figure 17−10 shows that five samples had been accumulated, and the con-
catenated result of the summation registers for the freeze−framed accumulate
& shift cycle, up to that point, was 0x00AE1479.
For this summation/shifter peripheral module, there is no possibility of an
overflow—even in the accumulate mode or cycle—because the worst-case
sample data value is 0x00FFFFFF (a 24-bit value), and the worst-case
accumulate or multiply count is 256. This makes the worst-case accumulate
result 0xFFFFFFFF. This worst-case scenario is comfortably accommodated
because the summation register is 32 bits wide.
Please refer to Section 12.13, Summation/Shifter Register, for more detailed
information.
17.8.1 ADC/Summation/Shifter Example
An example program has been provided to give you an insight into how to use
the ADC peripheral. In order to show how the 32-bit accumulator will work with
this module, a software implementation of the combination of the ADC fea-
tures and the summation/shifter features have been provided. The C code is
grafted into this section. In addition, a script file that runs in parallel with this
C code is also provided. This script file is also written in C.
The ADC peripheral is set up with the following features: V
REF
= 2.5V, Buff is
turned on and BOD (Burn Out Detect) is turned off by assigning a value of 0x20
to ADCON0. This register setting also selects an unity gain amplification for
the PGA. The bipolar option and the auto-filter options are selected through
ADCON1. Setting the value of register byte also makes the calibration selec-
tion. In this case, the reserved calibration option was selected. The decimation
ratio value of 0x00FF was assigned to the ACDON3:ADCON2 register pair.
Please refer to Chapter 12, Analog−to−Digital Converter, for more information
on the decimation ratio.
An ADC Conversion calibration is performed at the beginning of each data
conversion session. Calibration is initiated, and the processor enters an idle
state and stays there indefinitely, until the calibration process is completed.
When the converter calibration is completed, the ACC flag in the AISTAT SFR
is set. It is customary to discard the first 20 conversions after calibration.
The initialization of the summation/shifter is straightforward. A value of zero
must be written into the SSCON register. This action clears the contents of the
ACCR3, ACCR2, ACCR1 and ACCR0 SFRs. Then the proper SSCON value,
in this case 0xD2, is assigned. This assignment value sets the accumulate−
count, Acc_count, to eight, and the shift count value to eight. The accumulate
& shift option is also selected. This process of clearing and setting the value
of SSCON must be done at the beginning of every acc_count data accumula-
tion cycle, otherwise the previous accumulate & shift result is combined with
the next accumulate & shift data collection.