Texas Instruments MSC1210 User Manual

Page 185

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Hardware Configuration

15-3

Advanced Topics

15.1.1.1 Hardware Configuration Register 0 (HCR0)

Hardware configuration register 0 (HCR0) is used to configure the amount of
flash memory partitioned as data flash memory, configure the watchdog, and
set a number of security bits that restrict write access to flash memory.

The HCR0 has the following structure:

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

CADDR 7FH

EPMA

PML

RSL

EBR

EWDR

DFSEL2

DFSEL1

DSEL0

EPMA (bit 7)—Enable Program Memory Access (Security Bit). When this bit
is clear, flash memory cannot be read or written after the part is programmed. This
will prevent future updates to the firmware code. When the bit is set, which is the
default condition, flash memory will remain fully accessible for reprogramming.

PML (bit 6)—Program Memory Lock. When clear, your program may write
to flash program memory. When set, flash program memory is locked and can-
not be changed by your program. This may be set to ensure that the user pro-
gram does not overwrite the program itself by writing to flashmemory.

RSL (bit 5)—Reset Sector Lock. When clear, your program may write to the
reset sector (the first 4k of flash program memory). When it is set (default), your
program may not write to this area of flash memory. This bit functions the same
as the PML bit, but applies to only the first 4k of flash program memory. If the
MSC1210 is configured such that only 4k is assigned to flash program
memory, this bit has the same effect as setting PML.

EBR (bit 4)—Enable Boot ROM.

EWDR (bit 3)—Enable Watchdog Reset. When this bit is clear, a watchdog
situation provokes a watchdog auxiliary interrupt that your program needs to
intercept and handle. If this bit is set, a watchdog situation provokes a reset
of the MSC1210.

DFSEL2/DFSEL1/DFSEL0 (bits 2-0)—Flash Data Memory Size. These
three bits, together, select how much of the available flash memory will be as-
signed to data memory; the rest will be assigned to flash program memory.

DFSEL2/1/0

Amount of Flash Data Memory

001

32k

010

16k

011

8k

100

4k

101

2k

110

1k

111

No flash memory (default)

Note:

If more flash data memory is selected than flash memory exists on the actual
part, all of the flash memory available will be partitioned as flash data
memory, leaving nothing for flash program memory.

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