Texas Instruments MSC1210 - Manual (Page 112)

Polling Sequence
10-6
Each of the MSC1210 interrupts has its own enable bit in one of these three
SFRs. Enable a given interrupt by setting the corresponding bit. For example,
to enable the Timer 1 Interrupt, execute either:
MOV IE,#08h
or
SETB ET1
Both of the previous instructions set bit 3 of IE, thus enabling the Timer 1 Inter-
rupt. Once the Timer 1 Interrupt is enabled, whenever the TF1 bit is set, the
MSC1210 will automatically put on hold the main program and execute the
Timer 1 interrupt handler at address 001B
H
.
However, before the Timer 1 interrupt (or any other interrupt) is truly enabled, bit
7 of IE must also be set. Bit 7, the global interrupt enable/disable, enables or dis-
ables all interrupts simultaneously (except the auxiliary interrupts). That is to say,
if bit 7 is cleared, no interrupts will occur, even if all the other bits of IE are set.
Setting bit 7 will enable all the interrupts that have been selected by setting one
of the other enable bits in one of the three SFRs. This is useful in program execu-
tion if there is time-critical code that needs to be executed. In this case, the code
may need to be executed from start to finish without any interrupts getting in the
way. To accomplish this, simply clear bit 7 of IE and (CLR EA) bit 5 of EICON (CLR
EAI), and then set them after the time-critical code is done.
To sum up what has been stated in this section, to enable the Timer 1 Interrupt,
the most common approach is to execute the following two instructions:
SETB ET1 ;Enable Timer 1 Interrupt
SETB EA ;Enable Global Interrupt flag
Thereafter, the Timer 1 interrupt handler at 01B
H
will automatically be called
whenever the TF1 bit is set (upon Timer 1 overflow).
10.4 Polling Sequence
The MSC1210 automatically evaluates whether an interrupt should occur after
every instruction. When checking for interrupt conditions, under default condi-
tions, it checks them in the order as they appear in Table 10−1.
This means that if a serial interrupt occurs at the exact same instant that an exter-
nal 0 interrupt occurs, the external 0 interrupt will be executed first, and the serial
interrupt will be executed once the external 0 interrupt has completed.