Texas Instruments MSC1210 - Manual (Page 235)

Timers
17-7
Keil Simulator
The following is a listing of the C code used to demonstrate the timing and inter-
rupting features of Timer/Counters 0 and 1.
The included statements on the first three lines are the conventional ANSI C
include statements for adding the contents of different header files to a C pro-
gram. There are four routines including the main ( ) program that are needed
to run this program. They are described in the following paragraphs.
#include ”MSC1210.h”
#include <math.h>
#include <stdio.h>
long int timer_0_overflow_count;
int count_start;
char end_test;
void interrupt_timer0 ( );// interrupt 1;// using 1
*********************************setport ( )*************************************
void setport (void)
{
P3DDRL &= 0xf0;
P3DDRL |= 0x07; //P30 input, P31 output
TF2 = CLEAR; T2 = CLEAR;
CKCON |= 0x20; // Set timer 2 to clk/4
RCAP2 = 0xffd9; //Set Timer 2 to Generate 57690 bps
//Initialize TH2:TL2 so that next clock generates first Baud Rate pulse
THL2=0xffff;
T2CON = 0x34; // Set T2 for Serial0 Tx/Rx baudgen
//SCON: Async mode 1, 8−bit UART, enable rcvr; TI=CLEAR, RI = CLEAR
SCON = 0x50;
PCON |= 0x80; // Set SMOD0 for 16X baud rate clock
}
***************************interrupt_timer 0 ( )*********************************
This is a type 1 interrupt, which implies that the vector address for this routine
is 0x0B. If an interrupt request is issued, and there is no other interrupt request
of higher priority pending, and neither is an ISR from an interrupt source of
higher priority being processed, the processor makes a subroutine call to the
vector address location 0x0B, from where it executes a long jump to the in-
tended ISR routine.
There is a counter variable of type LONG within this ISR that allows the system
to monitor the number of overflow interrupts serviced during the course of the
test. In addition, because Timer 0 is operating in mode 1, 16 bit timer with inter-
rupt on overflow, the original value of the TH0:TL0 register pair must be replen-
ished at the end of each overflow cycle. The system is globally interrupt dis-
abled at the beginning of the routine, and then globally interrupt enabled at the
end of the routine.