Texas Instruments MSC1210 - Manual (Page 170)

Data Transfers
13-8
The SPI Receive control register, SPIRCON (9C
H
), controls the data receive
operation. The receive buffer can be flushed with the write only RXFLUSH bit.
A flush operation changes the SPI receive pointer so that it points to the same
address as the FIFO IN pointer, and clears the receive counter. The receive
counter indicates the number of bytes that have been received. An interrupt
can be generated when the receive count equals or exceeds a chosen num-
ber. If the interrupt is not masked in the AISTAT register, the SPI received inter-
rupt will cause a AI interrupt. The PPIRQ register is used in the AI interrupt rou-
tine to determine the source of the interrupt. The SPI receive interrupt can be
monitored in the AISTAT register.
The SPI Transmit control register, SPITCON (9D
H
), controls the data transmit
operation. The transmit buffer can be flushed with the write only TXFLUSH bit.
A flush operation changes the SPI transmit pointer so that it points to the same
address as the FIFO OUT pointer, and clears the transmit counter. The trans-
mit counter indicates the number of bytes in the transmit buffer (FIFO and buff-
er). An interrupt can be generated when the transmit count is less than or equal
to a chosen number. If the interrupt is not masked in the AISTAT register, the
SPI transmit interrupt with cause a auxiliary interrupt. The SPI transmit inter-
rupt can be monitored in the AISTAT register.