Texas Instruments MSC1210 User Manual

Page 232

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Timers

17-4

17.2 Timers

The simulator peripheral timer has three timer/counter modules: Timers 0, 1,
and 2; a system timer module; and a watchdog module. The Timer/Counter 0
module is identical to the Timer/Counter 1, so we shall only describe the opera-
tions of Timer/Counter 0.

Figure 17−1. Timer/Counter 0 − Mode 2

The first of the two selection boxes provides a list of four timer-operating modes
upon activation, from which you are allowed to choose. The various timing modes
are discussed in the Chapter 8, Timers. The default mode is mode 0, the 13-bit
timer/counter mode. This selection properly updates the content of the TMOD on
the basis of the logic statuses of the M1 and M0 bits of the Timer Mode control
register (TMOD). The second selection box allows you to select between the tim-
er and the counter modes of operation. The result of the selection is also properly
reflected in the value displayed in the TMOD window, according to the status of
the C/T0 bit in the TMOD register. In the same vein, the TL0 and TH0 registers
are properly associated with the contents of the TL0 and TH0 windows within the
dialog. The logical states of the T0 pin (P3.4), TF0 (Timer/Counter 0 interrupt
flag), the TR0, INT0 and GATE bits of the TCON SFR for instance, are reflected
in the checked/cleared statuses of the T0 pin, TF0, TR0, GATE and INT0 check
box displays, respectively.

The interrupt trigger type is determined by the state of the IT0 bit within the TCON
register. Clearing this bit implies level triggering, and setting it implies falling edge
triggering. If the level triggering option is selected, care must be taken to make
sure that the state of the INT0 pin returns to a high state (non−active) before re-
turning from an ISR, otherwise the interrupt request will be reasserted. For most
intents and purposes, it is unrealistic that you would be able to switch the check
box INT0 on and off fast enough to avoid causing an unintended interrupt request.
For this reason, an edge triggered interrupt option is recommended for simula-
tion. Whatever the case may be, both trigger types are accommodated and imple-
mented in this simulation package.

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