Texas Instruments MSC1210 - Manual (Page 135)

PWM Generator
11-11
Pulse Width Modulator/Tone Generator
11.3.3 Example of Updating PWM
Both PWM Period and PWM Duty, set via the PWMHI and PWMLOW SFRs,
are double-buffered. Their values are loaded to the 16-bit down counter and
16-bit PWMTemp register, respectively, when the counter expires.
PWM Period and PWM Duty may be renewed anytime during a PWM cycle.
The newly updated values are effective on the next PWM cycle. Double−buff-
ered operation is depicted in Figure 11−6.
PWM Period is accessed via the two 8-bit SFRs, PWMHI and PWMLOW. It is
possible that while you are updating one of these two SFRs at the transition
of two PWM cycles, PWM Period and PWM Duty are loaded to the counter
PWMTemp. As a result, only a partial PWM Period or PWM Duty is updated.
For those applications that need to avoid incomplete updates, the microcon-
troller could busy poll the P3.3 line to detect the transition of two PWM cycles
and update the PWM SFRs after the transition is finished. However, busy poll-
ing will use up a high percentage of CPU time.
The INT1 ISR can be used to detect the PWM cycle transition and update the
PWM SFRs at the appropriate time because P3.3 is fed back to the CPU as
INT1. This is illustrated in the following program example:
Figure 11−6. PWM Timing