Texas Instruments MSC1210 User Manual
Page 26
High-Performance Peripherals
1-14
1.7
High-Performance Peripherals
High-performance peripherals are included on-chip, which offload CPU proc-
essing and control functions from the core to further improve the overall device
efficiency and throughput. On-chip peripherals include additional SRAM, a
32-bit accumulator, an SPI-compatible serial port with a FIFO buffer, dual
USARTs, on-chip power-on reset, brownout reset, low-voltage detect, multiple
digital ports with configurable I/O, a 16-bit pulse width modulator (PWM), a
watchdog timer, and three timer/counters.
For instance, the SPI interface uses a FIFO buffer, which allows for the serial
transmission and reception of data with virtually no CPU overhead. The FIFO
buffer function allows for the transfer of large amounts of data at faster transfer
rates than more conventional methods.
Additionally, the 32-bit accumulator significantly reduces the processing over-
head for the multiple byte data from the ADC or other sources. This allows for
24-bit addition, subtraction, and shifting to be accomplished without using
CPU resources. This can reduce both the code size and code execution time.