Texas Instruments MSC1210 User Manual
Page 242
Watchdog Timer
17-14
/*
//For the actual device, the a logical AND of the content of the FRC0 SFR
register with 0xF7 must be performed to Disable the Watchdog Reset
so that the watchdog system can be controlled through the watchdog interrupt
facility.
CADDR = 0x7F;
CDATA &= ~0x08;
This must be done in the Parallel Programming mode, before the processor
starts up
*/
/*Turn Watchdog Timer On*/
PDCON |= 0x04;
/*Enable Watchdog Interrupt*/
EIE |= 0x10;
/*Set Watchdog Timer for 200 ms*/
WDTIMER = 0x0E;
/*Enable Watchdog Timer*/
WDTIMER |= 0x80;
WDTIMER &= ~0x80;
}
void watchdog_interrupt ( ) interrupt 12 using 1
{
/*This routine cannot be tested because we cannot get around the
watchdog reset on the simulator. The watchdog reset cannot be disabled.
The watchdog interrupt is never activated, hence, 0x0063 is never vectored
into.*/
static int
j;
/*Reset Watchdog. This is the sequential process of applying
Logic 1 followed by Logic 0*/
WDTIMER |= 0x20;
WDTIMER &= ~0x20;
/*Count Number of Resets*/
j++;
printf (”\nWatchdog Reset %d Times”, j);
/*Terminate watchdog Loop*/
watchdog_loop = 0;
}
void main(void)
{
int i, j;
setport ( );
init_watchdog ( );