Texas Instruments MSC1210 - Manual (Page 262)

Serial Peripheral Interface (SPI)
17-34
and the TXIRQ window determine the check/clear status of the SPIT check
box. As data is being received from the external device, the value of the re-
ceived data will be momentarily displayed in the SPIDATA window, and the
content of SPIRCON window is properly updated. In addition, as data is read
from the circular buffer, the value displayed in the SPIEND windows is properly
updated. The status of the SPIR bit is also updated on the basis of the values
displayed in the SPIRCON and RXIRQ windows.
A simple code example for a typical SPI communication exercise is appended.
17.11.1 SPI Sample Code
The following program simulates the data communication interaction between
two devices with SPI capabilities, where one operates in the master mode and
the other in the slave mode. Like the other example covered so far, a C style
program script was written using the
µ Vision 2’s debug functions protocol. This
program runs in parallel to the main program. The main program is set up as
the master, and the
µ
Vision 2’s debug functions package is set up as a slave.
The various SFRs that are pertinent to the SPI module are enabled and initialized.
The SPI peripheral is asserted as the master, and the communication speed is
specified. The receive and transmit buffers are flushed, and IRQ levels of four and
two are specified for the transmit and receive sections, respectively. The limits of
the circular buffer are defined as 0x0A and 0x0B. Finally, the SPI transmit and
receive interrupts are enabled, and the processor is globally interrupt enabled.
After having properly set up the I/O system for the Serial #1 window, and initial-
izing the interrupt enables and the SPI Communication system, this program
sends out a dummy data byte to start up the communication. The processor
then enters an infinite loop that is interrupted anytime there is an SPI transmit
or receive interrupt.
The SPIT flag is asserted whenever the transmitter IRQ level limit is not attained,
and the SPIR flag is asserted when the receive IRQ level is exceeded. Either con-
dition will generate a AI type interrupt. The transmit_receive ( ) ISR is called when-
ever this interrupt is acknowledged. As discussed earlier, the processor vectors
to address, 0x33, from which a long jump instruction is executed. The processor
branches to the appropriate section of the ISR routine on the basis of the value
contained in the AISTAT SFR. If the interrupt was caused by triggering the trans-
mit flag, SPIT, the processor branches into the transmit block of the ISR. If the
interrupt was caused by the receive flag, SPIR, the receive block will be selected.
Please refer to the chapter on SPI communication in this manual.
Within the receive block of the ISR, the processor reads the contents of the re-
ceive section of the circular buffer by reading the SPIDATA buffer continuously
until the SPIRCON count expired. The ISR resets the SPIR interrupt flag.
Within the transmit block of the ISR, the processor increments the value of the
static integer variable j and transmits its new value by writing it into the SPIDA-
TA SFR. The ISR resets the SPIT interrupt flag.
Upon completion of the associated ISR routine block, the process returns to
the infinite loop.