Texas Instruments MSC1210 - Manual (Page 255)

Summation/Shifter
17-27
Keil Simulator
In order to demonstrate how the summation/shifter handles the incremental
accumulation of sampled data, we have opted to enable both the ADC
conversion interrupt enable, EADC, and the summation interrupt enable,
ESUM, by assigning a value of 0x60 to the PIREG SFR. This implies that the
power fail interrupt, AI, is pulsed each time the ADC completes a sample
conversion on ADC, and each time the number of accumulation matches the
acc_count value on SUM. This means if a breakpoint were inserted in the
a_to_d_interrupt ISR routine for each data averaging cycle, eight samples in
this case, the value displayed in the non-editable text window associated with
acc_Count of the summation/shifter peripheral increase from 0 to 7 each time
the ADC interrupt is pulsed. The data values in the summation registers vary
as well, with the accumulation of conversion data results. On the eighth sample
of the cycle, when the SUM interrupt has been pulsed, the value content of the
non-editable display window rolls over from 7 to 0, and the contents of the
summation registers will be properly adjusted for the result of the eight data
sample averaging. Right after the averaged data has been successfully read,
the summation registers must be reset to all zeroes so it can start the next
batch of eight sample averaging with a clean slate. This can be most
conveniently achieved by assigning a 0x00 value to the SSCON SFR.
However, in this case, the contents of this register must be replenished with
the previous value of 0xD2, in order to properly set the operating parameters
for the summation/shifter module. This is equivalent to calling the
init_accumulator subroutine. These processes are repeated 64 times, after
which the simulator jumps into an infinite loop.
Note:
if we are not particularly interested in studying the individual data
accumulation step, we can assign a value of 0x40 to the PIREG SFR. In this
case, the AI interrupt ISR is called only when the SUM interrupt is triggered.
Snapshots of the summation/shifter peripheral and the ADC peripheral mid-
stride a typical 8-sample averaging block are shown in Figure 17−11 and
Figure 17−12. In the ADC Conversion peripheral, the AIN0 window shows that
the input voltage value of the most recent ADC conversion is 1.399994V. This
is a result of the 1.4V value set from the debugging script program. The 24-bit
conversion of this AIN0 value is displayed in the editable window labeled
ADRESH/M/L. The digital value of this conversion is 0x74B166. The non-edit-
able text window associated with acc count shows that four out of eight sam-
ples have been accumulated in the summation registers, and thus far, the sum
of all four accumulated 24-bit conversion values is 0x01D2F198.