GE Industrial Solutions Entellisys 5.0 Integrator's Guide - Manual (Page 20)

Control Features 20
1.6.1 Example of Long Time / Short Time Pickup alarm status in 3rd party
supervisory systems
In Entellisys there are many alarms including LT and ST pickup. An alarm will be active for as
long as the condition exists. The Acknowledge will persist until the user interacts with the HMI.
(See Figure 1-7)
In the case of trip alarms such as ST or LT Trip Status the alarm bit will only be active for the
period of time between trip and dropout. Often only a few milliseconds in duration while the
breaker is opening. During that time, however, it will set both the Alarm and its associated
Acknowledge bit high.
Figure 1-7 Entellisys Pickup Alarm and Status Timing Diagram. The alarm bits stay high only while the breaker is
opening and is clearing the fault. As soon as the fault is cleared, the relay will drop out. The ackowledge bit will
persist.
1.6.1.1 Implementation
The alarm registers are listed in Section 4 on page 62 . They are defined as data format code
F722 is defined as 2 registers containing breaker status for breaker 1 – 30. (See Section 5 on
page 152 )
For example, the LT Over current Trip Alarm State is two registers long. The first, register
x0464, contains information on breakers 17-30 and the second, register x0465, contains
information on breakers 1-16.
In Figure 1-8, the bits of the two registers are arranged left to right. In the example below,
breaker 1 (right most bit) and 30 (3rd from the left) tripped on ST, thus the ST Ack and ST Trip
Alarm registers will be updated to reflect the bit pattern below.
Figure 1-8 Short Time bit array. Read from left to right or MSB to LSB
The ST Trip Alarm State registers will only reflect the Trip condition while the breaker is opening.
During that time, the ST Trip Alarm state (x0468 and x0469) will read 8192 and 1 as will and ST
Ack registers.
After the fault has cleared and the Relays have dropped out, the ST Trip Alarm registers will clear
and the Acknowledge will persist.