Rockwell Automation 1746-HSCE,D17466.5 High-Speed Counter Module User Manual
Page 100
Publication 1746-UM006B-EN-P - August 2005
4-40 Configuration and Programming
I:e.0 Bit 6 - Sequence Done
This bit is set whenever the end of sequence is reached. This bit is set
(and remains set) as long as the last preset output data is in effect.
This bit is cleared when the last preset output data is not in effect.
I:e.0 Bits 7,8,9
Bits 7, 8, and 9 are reserved and must be reset to 0.
I:e.0 Bit 10 - Critical Error
This bit is set (to 1) whenever a Critical Error is detected that causes
the module operation to halt (even though the Function Control Bit is
set to 1) and module controlled outputs are turned OFF.
The errors are:
•
Module Configuration Errors (fault LED flashes)
•
Linear Counter Overflow/Underflow (fault LED remains off)
The error bit is cleared when the Function Control Bit is toggled to 0,
then back to 1.
Sequence Done (bit 6)
Cause
0
preset is valid
1
end of sequence
Critical Error (bit 10)
Cause
0
no critical error detected
1
critical error detected