Rockwell Automation 1746-HSCE,D17466.5 High-Speed Counter Module - Manual (Page 87)

Publication 1746-UM006B-EN-P - August 2005
Configuration and Programming 4-27
M0:e.1 Bit 2 - Counter Hold (Dynamic)
When set to 1, this bit prevents the pulse counter from counting input
pulses. In addition, the Pulse Counter State bits in the Status Word
(I:e.0/14-15) are set to Hold.
The Counter Reset function and Rate Measurement are not affected
when the Counter Hold bit is set.
M0:e.1 Bit 3 - Up/Down Count Direction (Dynamic)
This bit allows you to control the direction of the count when the
Pulse and Direction with Internal Control Input Type (M0:e.1/9-11) is
selected. This bit has no meaning when any other input type is
selected.
M0:e.1 Bit 4 - Soft Reset (Dynamic)
The Soft Reset bit can be used to reset the counter in combination
with the physical reset signals. Setting this bit (to 1) resets the counter,
via the Reset Mode bits, if Soft Reset (bit 7) is selected. The 0 to 1
transition of the Soft Reset condition (M0:e.1/5-7) resets the counter
when configured to do so (refer to Counter Reset Control in
Chapter 2).
Counter Hold (bit 2) Pulse Counter State
0 pulses are passed to the pulse counter
1 pulses are ignored
Up/Down Count
Direction (bit 3) Affect on Accumulated Count
0 accumulated count decrements with each count received in Input A
1 accumulated count increments with each count received in Input A
IMPORTANT
The Soft Reset bit must be held at 1 until the counter
resets. The Reset Input bit (I:e.0/12) can be used to
detect a counter reset.
Setup and Control Word, Word 1
Bit Number (decimal) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Resets Counter via
Soft Reset
Enables Soft Reset
M0:e.1 R R R