Rockwell Automation 1746-HSCE,D17466.5 High-Speed Counter Module - Manual (Page 159)

Publication 1746-UM006B-EN-P - August 2005
M0 and M1 Files B-5
The following table shows the expected maximum access times per
instruction or word of data for the SLC 5/02, SLC 5/03, SLC 5/04, and
SLC 5/05 processors.
SLC 5/02 Processor Examples
Processor Instruction Type Access Time per Bit
Instruction or Word of
Data Access Time per
Multi-Word
Instruction
SLC 5/02 Series B
All types
(1) 1930 µs 1580 µs plus 670 µs per
word
SLC 5/02 Series C All types 1157 µs 950 µs plus 400 µs per
word
SLC 5/03 (All Series) XIC or XIO 782 µs -
OTU, OTE, or OTL 925 µs -
COP to M file - 772 µs plus 23 µs per
word
COP from M file - 760 µs plus 22 µs per
word
FLL - 753 µs plus 30 µs per
word
MVM to M file 894 µs -
any source or Destination M file address 730 µs -
SLC 5/04 and SLC 5/05
(All Series) XIC or XIO 743 µs -
OTU, OTE, or OTL 879 µs -
COP to M file - 735 µs plus 23 µs per
word
COP from M file - 722 µs plus 22 µs per
word
FLL - 716 µs plus 30 µs per
word
MVM to M file 850 µs -
any source or Destination M file address 694 µs -
(1) Except the OSR instruction and the instruction parameters noted in Restrictions on Using M0-M1 Data File Addresses in this appendix.
SLC 5/02 Processor Example
] [
M0:2.1
1
]/[
M1:3.1
1
( )
M0:2.1
10
MOV
MOVE
Source
M1:10.7
Dest N7:10