Rockwell Automation 1746-HSCE,D17466.5 High-Speed Counter Module - Manual (Page 65)

Publication 1746-UM006B-EN-P - August 2005
Configuration and Programming 4-5
M0:e.1 Bit 2 - Counter Hold (Dynamic)
When set to 1, this bit prevents the pulse counter from counting input
pulses. In addition, the Pulse Counter State bits in the Status Word
(I:e.0/14-15) are set to Hold.
The Counter Reset function and Rate Measurement are not affected
when the Counter Hold bit is set.
M0:e.1 Bit 3 - Up/Down Count Direction (Dynamic)
This bit allows you to control the direction of the count when the
Pulse and Direction with Internal Control Input Type (M0:e.1/9-11) is
selected. This bit has no meaning when any other input type is
selected.
Counter Hold (bit 2) Pulse Counter State
0 Pulses are passed to the pulse counter
1 Pulses are ignored
Up/Down Count
Direction (bit 3) Affect on Accumulated Count
0 Accumulated Count decrements with each count received on Input A
1 Accumulated Count increments with each count received on Input A