Rockwell Automation 1746-HSCE,D17466.5 High-Speed Counter Module - Manual (Page 80)

Publication 1746-UM006B-EN-P - August 2005
4-20 Configuration and Programming
I:e.0 Bit 13 - Overflow/Underflow
When this bit is set, it indicates that the linear counter has overflowed
or underflowed. The module controlled outputs are reset to 0 while
this error is present.
The bit can be cleared by toggling the Function Control Bit
(M0:e.1/12) to 0 and then back to 1. This is a Critical Error.
I:e.0 bits 14 and 15 - Pulse Counter State
These bits indicate the current state of the Pulse Counter (the state of
the Rate Counter is separate):
I:e.1 Accumulated Count
This is the input value from the pulse counter. It gives the total
number of counts since the pulse counter was last reset (plus the reset
value).
Overflow/Underflow (bit 13) Cause
0 No overflow/underflow detected
1 Linear counter has overflowed or underflowed
Pulse Counter State Bits Pulse Counter State
15 14
0 0 stopped
0 1 running
1 0 undefined
1 1 hold
Bit Number (decimal) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Accumulated Count, Word 1 I:e.1