Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 106)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 106
5.1.1 Product ID
This read-only register identifies the board as ATCA-9305, and is used for PLD coding.
0x58 LFTR1 Low Frequency Timer 1 118
0x5C LFTR2 Low Frequency Timer 2 118
0x60 RGSR RTM GPIO State 119
0x64 RGCR RTM GPIO Control 119
0x68 RTMCR RTM Control 120
0x70 CMUL1 Cavium 1 C_MUL Clock Divisor Control 121
0x74 CMUL2 Cavium 2 C_MUL Clock Divisor Control 121
0x78 JTAG Altera JTAG Chain Software Control 122
0x80 CGCR Cavium GPIO Control 123
0x84 CGDO Cavium GPIO Data Out 123
0x88 CGDI Cavium GPIO Data In 124
0x8C IGCR IPMP/IPMC GPIO Control 125
0xD0 LPC1 Low Pin Count (LPC) Bus Control 125
0xD4 LPCD LPC Data 126
0xD8 SIRQI1 Serial IRQ Interrupt 1 [15:8] 126
0xDC SIRQI2 Serial IRQ Interrupt 2 [7:0] 127
Table 5-1 PLD Register Summary (continued)
Address Offset
(hex)
Mnemonic Register Name See Page
Scratch 1 (0x40) is a read/write register for storage only.
Table 5-2 Product ID (0x00)
Bits Function Description
7 CAVF1 Cavium Frequency 1
6 CAVF0 Cavium Frequency 0