Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 111)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 111
5.1.8 Reset Event
This read-only register contains the bit corresponding to the most recent event which caused
a reset. When power is first applied, the FP_PSH_BUTTN reset event is not latched into the
Reset Event register, this is the Power-on Reset (POR) event. Front panel reset events which
occur after power-up will be latched.
3 DEBUGLED3 LED CR22
2 DEBUGLED2 LED CR21
1 DEBUGLED1 LED CR19
0 DEBUGLED0 LED CR18
Table 5-8 LED (0x1C) (continued)
Bits Function Description
At power-up, the FRST_PWR_UP defaults to 1.
Table 5-9 Reset Event (0x20)
Bits Function Description
7 RTMPB RTM push button
6 SHR Software Hard Reset Set to 1 when the last reset was caused by a
write to the Reset Command register
5 CPUHRR CPU Hard Reset Request
4 COPSR Set to 1 when a COP header or software-issued Soft Reset (SRESET)
has occurred
3 COPHR Set to 1 when a COP header Hard Reset (HRESET) has occurred
2 PAYR Set to 1 when a Payload Reset from the IPMC has occurred
1 SBR Software Board Reset
Set to 1 when the IPMC software issued the board (payload) reset