Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 109)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 109
5.1.5 Hardware Configuration 0
The read-only HCR0 allows the MPC8548 monitor software to easily determine specific
hardware configurations, such as the processor clock and MPC8548 DDR memory.
5.1.6 Jumper Settings
These read-only bits may be read by software to determine the current jumper settings. See
the jumper descriptions on
Page No 61 .
1 CCBSYS1 SYSCLOCK1 to CCB clock ratio
0 CCBSYS0 SYSCLOCK0 to CCB clock ratio
Table 5-5 PLL Reset Configuration (0x0C) (continued)
Bits Function Description
Table 5-6 Hardware Configuration 0 (0x10)
Bits Function Description
7 0
6 P33P P33 (StrataFlash) is Present
5 RST_IND_CLR Clear the Reset Indication to the IPMC controller
4 CAVF1 Cavium Frequency 1
3 CAVF0 Cavium Frequency 0
2 PQCF1 MPC8548 Core Frequency 1
1 PQCF0 MPC8548 Core Frequency 0
0 PQDDRF
MPC8548 DDR SDRAM Fast
Table 5-7 Jumper Settings (0x18)
Bits Function Description
7 0
6 0
5 0