Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 126)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 126
5.1.30 LPC Data
This is the data register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU. This register provides the data to be sent or received,
depending upon the commands given in the control register.
5.1.31 Serial IRQ Interrupt 1
This is interrupt register1 for the LPC bus.
6 LPCS LPC State (internal use only)
5
4
3
2 LPCIOE LPC I/O Error
1 SYNCE SYNC Error
0 SYNCT SYNC Time-out
Table 5-30 LPC Bus (0xD0) (continued)
Bits Function Description
Table 5-31 LPC Data (0xD4)
Bits Function Description
7:0 - LPC Data
Table 5-32 Serial IRQ Interrupts 1 (0xD8)
Bits Function Description
7:0 - Interrupts