Verilink DIDCSU 2912 (880-502646-001) Product Manual - Manual (Page 60)

DIDCSU T1 Version
3-20 Verilink DIDCSU 2912 User Manual
Tn Test Pattern: Use this option to indicate one of the following options:
• None: This option indicates that no test pattern will be used.
• 3 in 24: Use 3-in-24 ONEs test pattern which consists of three pulses
in every 24-bit sequence (10001000 10000000 00000000). This
stress test is useful for testing circuits under extremely low density
conditions. This is mostly useful for T1 AMI.
• QRSS: Use Quasi-Random Signal Sequence that limits the signal to a
maximum of 15 zeros that can be transmitted sequentially. These
signals contain a medley of 20-bit words (except for more than 15
consecutive 0s). It repeats every 1,048,575 bits. Also, it contains
high density sequences and low density sequences, and sequences
that change from low density to high density and vice versa (as
defined by ANSI T1.403).
• 2
20
-1 : This pattern tests circuits for equalization and timing. It is the
same as QRSS, but without the 15 zeros restriction.
• 1/8: This pattern tests the ability of a circuit to support a pattern
having the minimum ones density (containing 7 zeros indicating
empty pulses and 1 pulse-1000000). It helps discover a timing
recovery problem. This is mostly useful for T1 AMI.
• 2
15
-1 : This pattern tests circuits for equalization and timing using
an alternate pattern for jitter testing. The pattern repeats every
32,757 bits.
• All 0s: This pattern is composed entirely of framed zeros
(00000000). It is only a valid bit pattern on a B8ZS T1, since it
violates the ones density rule for AMI T1s. It is suggested that all
B8ZS T1 circuits be tested, at least briefly, with this pattern to verify
the correct optioning of T1 facility components.
• 55 Octet: The Daly 55 octet pattern is used to test circuits for line
card and timing recovery. By rapidly transitioning from a long
sequence of low density octets to high density octets, the circuit is
stress tested.
• All 1s: This pattern is composed entirely of framed ones
(11111111). It stresses circuits by maximizing power consumption.
1) NONE
2) 3/24
3) QRSS
4) 2N20-1
5) 1/8
6) 2N15-1
7) ALL 0’S
8) 55 OCTET
(Daly)
9) ALL 1’S
An Send Line Loopback Bit-Oriented Protocol (LLB BOP): Sends a request
for a Line Loopback to the far-end CSU in the FDL portion of the ESF T1
framing. This option will only work if the Facilities Data Link is
continuous from near to far site. If a DACS or network design causes a
loss of FDL connectivity end-to-end, use the “Send Inband Loop Code”
command instead.
Use this option for FDL loopbacks to test the T1 from the near-end
toward the far-end.
1) DEACTIVATE
2) ACTIVATE
Bn Send Payload Loopback Bit-Oriented Protocol (PLB BOP): Sends a
request for a Payload Loopback to the far-end CSU in the FDL portion
of the ESF T1 framing. This option will only work if the Facilities Data
Link is continuous from near to far site.
1) DEACTIVATE
2) ACTIVATE
In Send Inband Loop Code: Sends a request for a remote CSU loop in the
timeslots of the selected network port. This loop works on D4 framed
T1 circuits and point-to-point ESF framed T1 circuits which pass
through a digital access and cross-connect system (DACS).
1) DEACTIVATE
2) ACTIVATE
En Reset Test Counter: This option resets the test counter to 0. The
counter is automatically reset when changing patterns.
X Exit the T1 Port Diagnostics Menu .
Command Description Options