Data port diagnostics menu, Data port diagnostics menu -18 – Verilink DIDCSU 2912 (880-502646-001) Product Manual User Manual

Page 90

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DIDCSU E1 Version

4-18

Verilink DIDCSU 2912 User Manual

Data Port

Diagnostics

Menu

For diagnostics on the data port, enter “P” to access the Data Port
Diagnostics Menu. Commands on this menu activate or deactivate
loops from both the data equipment to the DIDCSU data port and
back to the data equipment, and from the network to the data port
and back to the network.

Tn

Test Pattern: Use this option to indicate one of the following options:

• None: This option indicates that no test pattern will be used.

• 3 in 24: Use 3-in-24 ONEs test pattern which consists of three pulses

in every 24-bit sequence (10001000 10000000 00000000). This

stress test is useful for testing circuits under extremely low density

conditions.

• QRSS: Use Quasi-Random Signal Sequence that limits the signal to a

maximum of 15 zeros that can be transmitted sequentially. These

signals contain a medley of 20-bit words (except for more than 15

consecutive 0s). It repeats every 1,048,575 bits. Also, it contains high

density sequences and low density sequences, and sequences that

change from low density to high density and vice versa (as defined by

ANSI T1.403).

2

20

-1

: This pattern tests circuits for equalization and timing. It is the

same as QRSS, but without the 15 zeros restriction.

• 1/8: This pattern tests the ability of a circuit to support a pattern

having the minimum ones density (containing 7 zeros indicating

empty pulses and 1 pulse-1000000). It helps discover a timing

recovery problem.

2

15

-1

: This pattern tests circuits for equalization and timing using an

alternate pattern for jitter testing. The pattern repeats every 32,757

bits.

• All 0s: This pattern is composed entirely of framed zeros (00000000).

• 55 Octet: The Daly 55 octet pattern is used to test circuits for line

card and timing recovery. By rapidly transitioning from a long

sequence of low density octets to high density octets, the circuit is

stress tested.

• All 1s: This pattern is composed entirely of framed ones (11111111).

It stresses circuits by maximizing power consumption.

1) NONE

2) 3/24

3) QRSS

4) 2N20-1

5) 1/8

6) 2N15-1

7) ALL 0’S

8) 55 OCTET

(Daly)

9) ALL 1’S

X

Exit the

E1 Port Diagnostics Menu

Command

Description

Options

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