Maxim Integrated DS21Q55 - Manual (Page 10)

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22.3.4 Receive Packet Bytes Available ...............................................................................................144
22.3.5 HDLC FIFOS....................................................................................................................................145
22.4 R ECEIVE HDLC C ODE E XAMPLE ............................................................................................................. 146
22.5 L EGACY FDL S UPPORT (T1 M ODE )......................................................................................................... 146
22.5.1 Receive Section ..............................................................................................................................146
22.5.2 Transmit Section.............................................................................................................................148
22.6 D4/SLC– 96 O PERATION ............................................................................................................................ 148
23. LINE INTERFACE UNIT (LIU)................................................................................................................149
23.1 LIU O PERATION .......................................................................................................................................... 150
23.2 LIU R ECEIVER ............................................................................................................................................. 150
23.2.1 Receive Level Indicator............................................................... Error! Bookmark not defined.
23.2.2 Receive G.703 Synchronization Signal (E1 Mode)............................................................151
23.2.3 Monitor Mode...................................................................................................................................151
23.3 LIU T RANSMITTER ..................................................................................................................................... 152
23.3.1 Transmit Short-Circuit Detector/Limiter..................................................................................152
23.3.2 Transmit Open-Circuit Detector ................................................................................................152
23.3.3 Transmit BPV Error Insertion .....................................................................................................152
23.3.4 Transmit G.703 Synchronization Signal (E1 Mode) ...........................................................152
23.4 MCLK P RESCALER ..................................................................................................................................... 153
23.5 J ITTER A TTENUATOR .................................................................................................................................. 153
23.6 CMI (C ODE M ARK I NVERSION ) O PTION ................................................................................................. 153
23.7 LIU C ONTROL R EGISTERS ......................................................................................................................... 154
23.8 R ECOMMENDED C IRCUITS ......................................................................................................................... 164
23.9 C OMPONENT S PECIFICATIONS ................................................................................................................... 166
24. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION................170
25. BERT FUNCTION .......................................................................................................................................177
25.1 BERT R EGISTER D ESCRIPTION ................................................................................................................. 178
25.2 BERT R EPETITIVE P ATTERN S ET ............................................................................................................. 183
25.3 BERT B IT C OUNTER .................................................................................................................................. 184
25.4 BERT E RROR C OUNTER ............................................................................................................................ 185
26. PAYLOAD ERROR INSERTION FUNCTION...................................................................................186
26.1 N UMBER O F E RROR R EGISTERS ............................................................................................................... 188
26.1.1 Number Of Errors Left Register ................................................................................................189
27. INTERLEAVED PCM BUS OPERATION...........................................................................................190
27.1 C HANNEL I NTERLEAVE M ODE .................................................................................................................. 190
27.2 F RAME I NTERLEAVE M ODE ....................................................................................................................... 190
28. EXTENDED SYSTEM INFORMATION BUS (ESIB)......................................................................193
29. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER......................................................197
30. FRACTIONAL T1/E1 SUPPORT ...........................................................................................................198
31. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT .........................199
31.1 I NSTRUCTION R EGISTER ............................................................................................................................. 203
31.2 T EST R EGISTERS .......................................................................................................................................... 205
31.3 B OUNDARY S CAN R EGISTER ..................................................................................................................... 205
31.4 B YPASS R EGISTER ...................................................................................................................................... 205
31.5 I DENTIFICATION R EGISTER ........................................................................................................................ 205
32. FUNCTIONAL TIMING DI AGRAMS ....................................................................................................208
32.1 T1 M ODE ...................................................................................................................................................... 208