Maxim Integrated DS21Q55 - Manual (Page 6)

Product Preview DS21Q55
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§ Hardware-signaling capability
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Receive-signaling reinsertion to a backplane, multiframe sync
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Availability of signaling in a separate PCM data stream
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Signaling freezing
§ Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
§ Access to the data streams in between the framer/formatter and the elastic stores
§ User-selectable synthesized clock output
1.1.7 HDLC Controllers
§ Two independent HDLC controllers
§ Fast load and unload features for FIFOs
§ SS7 support for FISU transmit and receive
§ Independent 128-byte RX and TX buffers with interrupt support
§ Access FDL, Sa, or single/multiple DS0 channels
§ DS0 access includes Nx64 or Nx56
§ Compatible with polled or interrupt-driven environments
§ Bit Oriented Code (BOC) support
1.1.8 Test and Diagnostics
§ Programmable on-chip Bit Error Rate Testing (BERT)
§ Pseudorandom patterns including QR
SS
§ User-defined repetitive patterns
§ Daly pattern
§ Error insertion single and continuous
§ Total-bit and errored-bit counts
§ Payload Error Insertion
§ Error insertion in the payload portion of the T1 frame in the transmit path
§ Errors can be inserted over the entire frame or selected channels
§ Insertion options include continuous and absolute number with selectable insertion rates
§ F-bit corruption for line testing
§ Loopbacks (remote, local, analog, and per-channel loopback)
1.1.9 Extended System Information Bus
§ Host can read interrupt and alarm status on up to eight ports with a single-bus read
1.1.10 Control Port
§ 8-bit parallel control port
§ Multiplexed or no nmultiplexed buses
§ Intel or Motorola formats
§ Supports polled or interrupt-driven environments
§ Software access to device ID and silicon revision
§ Software-reset supported
Automatic clear on power-up
§ Flexible register-space resets
§ Hardware reset pin