Maxim Integrated DS21Q55 User Manual
Page 82
Product Preview
DS21Q55
82 of 248
012103
Please contact
or search
http://www.maxim-ic.com
for updated
information.
15.1.1 Processor-Based Receive Signaling
The robbed-bit signaling (T1) or TS16 CAS signaling (E1) is sampled in the receive data stream and
copied into the receive signaling registers, RS1 through RS16. In T1 mode, only RS1 through RS12 are
used. The signaling information in these registers is always updated on multiframe boundaries. This
function is always enabled.
15.1.1.1 Change Of State
In order to avoid constant monitoring of the receive signaling registers, the DS21Q55 can be programmed
to alert the host whe n any specific channel or channels undergo a change of their signaling state. RSCSE1
through RSCSE4 for E1 and RSCSE1 through RSCSE3 for T1 are used to select which channels can
cause a change of state indicatio n. The change of state is indicated in Status Register 5 (SR1.5). If
signaling integration, CCR1.5, is enabled then the new signaling state must be constant for three
multiframes before a change of state indication is indicated. The user can enable the INT pin to toggle
low upon detection of a change in signaling by setting the IMR1.5 bit. The signaling integration mode is
global and cannot be enabled on a channel by channel basis.
The user can identity which channels have undergone a signaling change of state by reading the
RSINFO1 through RSINFO4 registers . The information from this registers will tell the user which RSx
register to read for the new signaling data. All changes are indicated in the RSINFO1–RSINFO4 register
regardless of the RSCSE1–RSCSE4 registers.
15.1.2 Hardware-Based Receive Signaling
In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin.
RSIG is a signaling PCM-stream output on a channel-by-channel basis from the signaling buffer. The
signaling data, T1 robbed bit or E1 TS16, is still present in the original data stream at RSER. The
signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be reinserted
into the original data stream in a different alignment that is determined by a multiframe signal from the
RSYNC pin. In this mode, the receive elastic store can be enabled or disabled. If the receive elastic store
is enabled, then the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF
framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The
RSIG data is updated once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the
AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6
contain the same data as bits 7 and 8 respectively in each channel. The RSIG data is updated once a
multiframe (1.5ms) unless a freeze is in effect. See the Functional Timing Diagrams for some examples.
15.1.2.1 Receive-Signaling Reinsertion at RSER
In this mode, the user will provide a multiframe sync at the RSYNC pin and the signaling data will be
reinserted based on this alignment. In T1 mode, this results in two copies of the signaling data in the
RSER data stream. The original signaling data based on the Fs/ESF frame positions and the realigned
data based on the user supplied multiframe sync applied at RSYNC. In voice channels this extra copy of
signaling data is of little consequence. Reinsertion can be avoided in data channels since this feature is
activated on a per-channel basis. For reinsertion, the elastic store must be enabled; however, the
backplane clock can be either 1.544MHz or 2.048MHz.
Signaling reinsertion mode is enabled, on a per-channel basis by setting the RSRCS bit high in the PCPR
register. The channels that are to have signaling reinserted are selected by writing to the PCDR1-PCDR3