Maxim Integrated DS21Q55 - Manual (Page 111)

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18.2 Transmit Side
See the IOCR1 and IOCR2 registers for information on clock and I/O configurations.
The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic
store is enabled a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. For higher rate
system-clock applications, see the Interleaved PCM Bus Operation section. Controlled slips in the
transmit elastic store are reported in the SR5.3 bit and the direction of the slip is reported in the SR5.4
and SR5.5 bits.
18.2.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER will be
ignored every fourth channel. Hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20,
24, and 28) will be ignored. The user can supply frame or multiframe sync pulse to the TSSYNC input.
Also, in 2.048MHz applications, the TCHBLK output will be forced high during the channels ignored by
the framer.
18.2.2 E1 Mode
A 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. The user must supply a frame-
sync pulse or a multiframe-sync pulse to the TSSYNC input.
18.3 Elastic Stores Initialization
There are two elastic-store initializations that can be used to improve performance in certain applications,
elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read
and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are
locked to RCLK/TCLK, respectively). See table below for details.
ELASTIC STORE DELAY AFTER INITIALIZATION Table 20-1
INITIALIZATION REGISTER BIT DELAY
Receive Elastic Store Reset
Transmit Elastic Store Reset ESCR.2
ESCR.6 8 Clocks < Delay < 1 Frame
1 Frame < Delay < 2 Frames
Receive Elastic Store Align
Transmit Elastic Store Align ESCR.3
ESCR.7 ½ Frame < Delay < 1 ½ Frames
½ Frame < Delay < 1 ½ Frames
18.4 Minimum-Delay Mode
Elastic store minimum-delay mode can be used when the elastic store’s system clock is locked to its
network clock (e.g., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for
the transmit side). ESCR.5 and ESCR.1 enable the transmit and receive elastic store minimum-delay
modes. When enabled the elastic stores will be forced to a maximum depth of 32 bits instead of the
normal two- frame depth. This feature is useful primarily in applications that interface to a 2.048MHz bus.
Certain restrictions apply when minimum delay mode is used. In addition to the restriction mentioned
above, RSYNC must be configured as an output when the receive elastic store is in minimum delay mode
and TSYNC must be configured as an output when transmit minimum delay mode is enabled. In a typical
application RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is
connected to TSSYNC (frame input mode). All of the slip contention logic in the framer is disabled
(since slips cannot occur). On power-up, after the RSYSCLK and TSYSCLK signals have locked to their