Maxim Integrated DS21Q55 - Manual (Page 212)

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RECEIVE SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled)
Figure 35-5
NOTES:
1) RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one.
2) RSYNC is in the output mode (IOCR1.4 = 0).
3) RSYNC is in the input mode (IOCR1.4 = 1).
4) RCHBLK is forced to one in the same channels as RSER (Note 1).
5) The F-bit position is passed through the receive-side elastic store.
RSER
CHANNEL 1
RCHCLK
RCHBLK
RSYSCLK
RSYNC
CHANNEL 31 CHANNEL 32
1
3
4
RSYNC
2
RMSYNC
RSIG
CHANNEL 31 CHANNEL 32
B A C/A D/B C/A D/B A B
CHANNEL 1
LSB MSB LSB