Maxim Integrated DS21Q55 - Manual (Page 150)

Product Preview DS21Q55
150 of 248 012103
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23.1 LIU Operation
The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is
transformer coupled into the RTIP and RRING pins of the DS21Q55. The user has the option to use
internal termination, software selectable for 75O/100O/120O applications, or external termination. The
LIU recovers clock and data from the analog signal and passes it through the jitter attenuation MUX
outputting the received line clock at RCLKO and bipolar or NRZ data at RPOSO and RNEGO. The
DS21Q55 contains an active filter that reconstructs the analog received signal for the nonlinear losses that
occur in transmission. The receive circuitry also is configurable for various monitor applications. The
device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the
device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at
TPOSI and TNEGI is sent via the jitter attenuation MUX to the wave shaping circuitry and line driver.
The DS21Q55 will drive the E1 or T1 line from the TTIP and TRING pins via a coupling transformer.
The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul
(DSX-1) lines for T1.
23.2 LIU Receiver
The DS21Q55 contains a digital clock recovery system. The device couples to the receive E1 or T1
twisted pair (or coaxial cable in 75O E1 applications) via a 1:1 transformer. See Table 25-1 for
transformer details. The DS21Q55 has the option of using software-selectable termination requiring only
a single, fixed pair of termination resistors.
The DS21Q55’s LIU is designed to be fully software selectable for E1 and T1 without the need to change
any external resistors for the receive-side. The receive-side will allow the user to configure the device for
75O, 100O, or 120O receive termination by setting the RT1 (LIC4.1) and RT0 (LIC4.0) bits. When
using the internal termination feature, the resistors labeled R in Figure should be 60O each. If external
termination is required, RT1 and RT0 should be set to zero and the resistors labeled R in Figure will need
to be 37.5O, 50O, or 60O each depending on the line impedance.
There are two ranges of receive sensitivity for both T1 and E1, which is selectable by the user. The EGL
bit of LIC1 (LIC1.4) selects the full or limited sensitivity.
The resultant E1 or T1 clock derived from MCLK is multiplied by 16 via an internal PLL and fed to the
clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times
over-sampler, which is used to recover the clock and data. This over-sampling technique offers
outstanding performance to meet jitter tolerance specifications shown in.
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1
AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the
receive path (as is the case in most applications), the jitter attenuator restores the RCLK to an
approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the
RCLK output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-sampled
digital clock recovery circuitry. See Receive AC Timing Characteristics for more details. When no signal
is present at RTIP and RRING, a receive carrier loss (RCL) condition will occur and the RCLK will be
derived from the JACLK source.