Maxim Integrated DS21Q55 - Manual (Page 219)

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RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled)
Figure 35-12
NOTES:
1) RCHBLK is programmed to block channel 1.
2) RLCLK is programmed to mark the Sa4 bit in RLINK.
3) Shown is a RNAF frame boundary.
4) RSIG normally contains the CAS multiframe-alignment nibble (0000) in channel 1.
CHANNEL 32 CHANNEL 1 CHANNEL 2
CHANNEL 32 CHANNEL 1 CHANNEL 2
RCLK
RSER
RSYNC
RFSYNC
RSIG
RCHCLK
RCHBLK
1
RLCLK
RLINK
2
C D A
LSB MSB
A B
Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
Sa4 Sa5 Sa6 Sa7 Sa8
B
Note 4