Maxim Integrated DS21Q55 - Manual (Page 152)

Product Preview DS21Q55
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23.3 LIU Transmitter
The DS21Q55 uses a phase- lock loop along with a precision digital-to-analog converter (DAC) to create
the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the transmitter meet
the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which waveform is to be
generated by setting the ETS bit (LIC2.7) for E1 or T1 operation, then programming the L2/L1/L0 bits in
register LIC1 for the appropriate application.
A 2.048MHz or 1.544MHz clock is required at TCLKI for transmitting data presented at TPOSI and
TNEGI. Normally these pins are connected to TCLKO, TPOSO and TNEGO. However, the LIU may
operate in an independent fashion. ITU specification G.703 requires an accuracy of ±50ppm for both T1
and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. The clock can be
sourced internally from RCLK or JACLK. See LIC2.3, LIC4.4 and LIC4.5 for details. Due to the nature
of the design of the transmitter, very little jitter (less than 0.005 UIpp broadband from 10Hz to 100kHz) is
added to the jitter present on TCLK. Also, the waveforms created are independent of the duty cycle of
TCLK. The transmitter couples to the E1 or T1 transmit twisted pair (or coaxial cable in some E1
applications) via a 1:2 step- up transformer. In order for the device to create the proper waveforms, the
transformer used must meet the specifications listed in Table 25-1. The DS21Q55 has the option of using
software-selectable transmit termination.
The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode,
the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the
automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the
network load. See the Transmit Line Build-Out Control (TLBC) register for details.
23.3.1 Transmit Short-Circuit Detector/Limiter
The DS21Q55 has automatic short-circuit limiter which limits the source current to 50mA (rms) into a 1
ohm load. This feature can be disabled by setting the SCLD bit (LIC2.1) = 1. TCLE (INFO2.5) provides
a real time indication of when the current limiter is activated. If the current limiter is disabled, TCLE will
indicate that a short-circuit condition exist. Status Register SR1.2 provides a latched version of the
information, which can be used to activate an interrupt when enable via the IMR1 register. When set low,
the TPD bit (LIC1.0) will power-down the transmit line driver and tristate the TTIP and TRING pins.
23.3.2 Transmit Open-Circuit Detector
The DS21Q55 can also detect when the TTIP or TRING outputs are open circuited. TOCD (INFO2.4)
will provide a real-time indication of when an open circuit is detected. SR1 provides a latched version of
the information (SR1.1), which can be used to activate an interrupt when enable via the IMR1 register.
23.3.3 Transmit BPV Error Insertion
When IBPV (LIC2.5) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion.
23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)
The DS21Q55 can transmit the 2.048MHz square-wave synchronization clock As defined in section 13 of
ITU G.703 10/98. In order to transmit the 2.048MHz clock, when in E1 mode, set the transmit
synchronization clock enable (LIC3.1) = 1.