Motorola ColdFire MCF5281 - Manual (Page 105)

Cache
Freescale Semiconductor 4-7
4.3 Functional Description
The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches from
the ColdFire core and certain memory fetches initiated by the debug module. Typically, the debug module's
memory references appear as supervisor data accesses but the unit can be programmed to generate
user-mode accesses and/or instruction fetches. The cache processes any fetch access in the normal manner.
4.3.1 Interaction with Other Modules
Because the cache and high-speed SRAM module are connected to the ColdFire core's local data bus,
certain user-defined configurations can result in simultaneous fetch processing.
Table 4-5. ACRn Field Descriptions
Field Description
31–24
AB
Address base. This 8-bit field is compared to address bits [31:24] from the processor's local bus under control of the
ACR address mask. If the address matches, the attributes for the memory reference are sourced from the given ACR.
23–16
AM
Address mask. Masks any AB bit. If a bit in the AM field is set, the corresponding bit of the address field comparison
is ignored.
15
EN
ACR Enable. Hardware reset clears this bit, disabling the ACR.
0 ACR disabled
1 ACR enabled
14–13
SM
Supervisor mode. Allows the given ACR to be applied to references based on operating privilege mode of the
ColdFire processor. The field uses the ACR for user references only, supervisor references only, or all accesses.
00 Match if user mode
01 Match if supervisor mode
1x Match always—ignore user/supervisor mode
12–7 Reserved, must be cleared.
6
CM
Cache mode.
0 Caching enabled
1 Caching disabled
5
BWE
Buffered write enable. Defines the value for enabling buffered writes. If BWE is cleared, the termination of an operand
write cycle on the processor's local bus is delayed until the system bus cycle is completed. Setting BWE terminates
the write cycle on the local bus immediately and the operation is then buffered in the bus controller. In this mode,
operand write cycles are effectively decoupled between the processor's local bus and the system bus.
Generally, the enabling of buffered writes provides higher system performance but recovery from access errors may
be more difficult.
For the V2 ColdFire core, the reporting of access errors on operand writes is always imprecise, and enabling buffered
writes simply decouples the write instruction from the signaling of the fault even more.
0 Writes are not buffered.
1 Writes are buffered.
4–3 Reserved, must be cleared.
2
WP
Write protect. Defines the write-protection attribute. If the effective memory attributes for a given access select the
WP bit, an access error terminates any attempted write with this bit set.
0 Read and write accesses permitted
1 Only read accesses permitted
1–0 Reserved, must be cleared.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3