Motorola ColdFire MCF5281 - Manual (Page 324)

Fast Ethernet Controller (FEC)
17-14 Freescale Semiconductor
To perform a read or write operation on the MII Management Interface, write the MMFR register. To
generate a valid read or write management frame, ST field must be written with a 01 pattern, and the TA
field must be written with a 10. If other patterns are written to these fields, a frame is generated, but does
not comply with the IEEE 802.3 MII definition.
To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register),
the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern causes
the control logic to shift out the data in the MMFR register following a preamble generated by the control
state machine. During this time, contents of the MMFR register are altered as the contents are serially
shifted and are unpredictable if read by the user. After the write management frame operation completes,
the MII interrupt is generated. At this time, contents of the MMFR register match the original value
written.
To generate an MII management interface read frame (read a PHY register), the user must write {01 10
PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a don’t care). Writing
this pattern causes the control logic to shift out the data in the MMFR register following a preamble
generated by the control state machine. During this time, contents of the MMFR register are altered as the
contents are serially shifted and are unpredictable if read by the user. After the read management frame
operation completes, the MII interrupt is generated. At this time, the contents of the MMFR register match
the original value written except for the DATA field whose contents are replaced by the value read from
the PHY register.
If the MMFR register is written while frame generation is in progress, the frame contents are altered.
Software must use the MII interrupt to avoid writing to the MMFR register while frame generation is in
progress.
Table 17-10. MMFR Field Descriptions
Field Description
31–30
ST
Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame.
29–28
OP
Operation code.
00 Write frame operation, but not MII compliant.
01 Write frame operation for a valid MII management frame.
10 Read frame operation for a valid MII management frame.
11 Read frame operation, but not MII compliant.
27–23
PA
PHY address. This field specifies one of up to 32 attached PHY devices.
22–18
RA
Register address. This field specifies one of up to 32 registers within the specified PHY device.
17–16
TA
Turn around. This field must be programmed to 10 to generate a valid MII management frame.
15–0
DATA
Management frame data. This is the field for data to be written to or read from the PHY register.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3