1 configuring the flexcan bit timing, 9 flexcan error counters, 1 configuring the flexcan bit timing -13 – Motorola ColdFire MCF5281 User Manual
Page 483: 9 flexcan error counters -13
FlexCAN
Freescale Semiconductor
25-13
25.4.8.1
Configuring the FlexCAN Bit Timing
The following considerations must be observed when programming bit timing functions.
•
If the programmed PRESDIV value results in a single system clock per one time quantum, then the
PSEG2 field in CANCTRL1 register should not be programmed to zero.
•
If the programmed PRESDIV value results in a single system clock per one time quantum, then the
information processing time (IPT) equals three time quanta, otherwise it equals two time quanta.
If PSEG2 equals two, then the FlexCAN transmits one time quantum late relative to the scheduled
sync segment.
•
If the prescaler and bit timing control fields are programmed to values that result in fewer than ten
system clock periods per CAN bit time and the CAN bus loading is 100%, anytime the rising edge
of a start-of-frame (SOF) symbol transmitted by another node occurs during the third bit of the
intermission between messages, the FlexCAN may not be able to prepare a message buffer for
transmission in time to begin its own transmission and arbitrate against the message which
transmitted the early SOF.
•
The FlexCAN bit time must be programmed to be greater than or equal to nine system clocks, or
correct operation is not guaranteed.
25.4.9
FlexCAN Error Counters
There are two error counters in the FlexCAN: transmit error counter (TXECTR), and receive error counter
(RXCTR). The rules for increasing and decreasing these counters are described in the CAN protocol, and
are fully implemented in the FlexCAN. Each counter comprises the following:
•
8 bit up/down counter
•
Increment by 8 (Rx_Err_Counter also by 1)
•
Decrement by 1
•
Avoid decrement when equal to zero
•
Rx_Err_Counter preset to a value 119
≤
x
≤ 127
•
Value after reset = zero
•
Detect values for Error Passive, Bus Off and Error Active transitions and for alerting the host.
Both counters are read only (except for Test/Freeze/Halt modes).
Table 25-7. Examples of System Clock/CAN Bit-Rate/S-Clock
System Clock
Freq (Mhz)
Can bit-rate
(Mhz)
Possible
S-Clock Freq
(Mhz)
Possible
number of
time-quanta/bit
Pre-Scaler
programed
value + 1
Comments
48
1
8,12,24
8,12,24
3,2,1
Min 8 time-quanta
Max 25 time-quanta
40
1
10,20
10,20
2,1
32
1
8,16
8,16
2,1
48
0.125
1,1.5,2,3
8,12,16,24
24,16,12,8
40
0.125
1,2,2.5
8,16,20
20,10,8
32
0.125
1,2
8,16
16,8
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3