1 uart mode registers 1 (umr1n), 1 uart mode registers 1 (umr1, 1 uart mode registers 1 (umr1 n ) – Motorola ColdFire MCF5281 User Manual

Page 425

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UART Modules

Freescale Semiconductor

23-5

23.3.1

UART Mode Registers 1 (UMR1n)

The UMR1n registers control UART module configuration. UMR1n can be read or written when the mode
register pointer points to it, at RESET or after a

RESET

MODE

REGISTER

POINTER

command using

UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.

IPSBAR

Offset:

0x00_0200 (UMR10)
0x00_0240 (UMR11)
0x00_0280 (UMR12)

Access: User read/write

1

7

6

5

4

3

2

1

0

R

RXRTS

RXIRQ/

FFULL

ERR

PM

PT

B/C

W

Reset:

0

0

0

0

0

0

0

0

1

After UMR1n is read or written, the pointer points to UMR2n

Figure 23-3. UART Mode Registers 1 (UMR1n)

Table 23-3. UMR1n Field Descriptions

Field

Description

7

RXRTS

Receiver request-to-send. Allows the URTSn output to control the UCTSn input of the transmitting device to prevent
receiver overrun. If the receiver and transmitter are incorrectly programmed for URTSn control, URTSn control is
disabled for both. Transmitter RTS control is configured in UMR2n[TXRTS].
0 The receiver has no effect on URTSn.
1 When a valid start bit is received, URTSn is negated if the UART's FIFO is full. URTSn is reasserted when the

FIFO has an empty position available.

6

RXIRQ/

FFULL

Receiver interrupt select.
0 RXRDY is the source generating interrupt or DMA requests.
1 FFULL is the source generating interrupt or DMA requests.

5

ERR

Error mode. Configures the FIFO status bits, USRn[RB,FE,PE].
0 Character mode. The USRn values reflect the status of the character at the top of the FIFO. ERR must be 0 for

correct A/D flag information when in multidrop mode.

1 Block mode. The USRn values are the logical OR of the status for all characters reaching the top of the FIFO since

the last

RESET

ERROR

STATUS

command for the UART was issued. See

Section 23.3.5, “UART Command

Registers (UCRn)

.

4–3

PM

Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character,
and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below.

MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3

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